In this work, we have performed Si and C isoelectronic implantations inn-type andvanadium(V) implantations inp-type 6H–SiC to obtain highly resistive regions. The compensation is achieved by the lattice damage created by the Si and C implantations and the chemically active nature of the V implant. For the Si and C implantations, the as-implanted resistivity initially increased with increasing implant fluence due to the introduction of compensating levels caused by the lattice damage, then decreased at higher fluences due to hopping conduction of the trapped carriers. The resistivity of the Si and C implanted material has been measured after isochronal heat treatments over the temperature range of 400–1000 °C. The maximum resistivity values measured for Si and C implanted and heat treated material were∼1012 &OHgr; cm.For the 700 °C V implantation inp-type SiC, resistivities of>1012 &OHgr; cmwere measured after 1500 or 1600 °C annealing to activate the V implant. Redistribution of the V implant is observed after annealing. ©1997 American Institute of Physics.