Bit-serial systolic sorting: general complexities and an implementation in VLSI
作者:
H.F.Li,
R.Jayakumar,
X.Sun,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1987)
卷期:
Volume 134,
issue 3
页码: 125-132
年代: 1987
DOI:10.1049/ip-e.1987.0022
出版商: IEE
数据来源: IET
摘要:
Bit-serial systolic sorting in very large scale integration (VLSI) is considered. Lower bounds on the area, computation time, and flush time for such a sorter are derived for three different input formats, namely the bitwise, the wordwise and the unconstrained formats. The logic design and CMOS circuit design of an optimal bit-serial wordwise systolic sorter are presented. The performance characteristics of the designed chip are discussed.
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