Pipeline prime-factor DFT for VLSI using cyclic shuffling
作者:
H.C.Shyu,
T.K.Truong,
I.S.Reed,
I.S.Hsu,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1987)
卷期:
Volume 134,
issue 5
页码: 247-253
年代: 1987
DOI:10.1049/ip-e.1987.0041
出版商: IEE
数据来源: IET
摘要:
The fast prime-factor discrete Fouriertransform (DFT) algorithm [2–4] can be used to reduce the number of basic cells when the transform length of a DFT is not a highly composite number. This pipeline prime-factor DFT can be realised by a one-to r-dimensional index mapping by (r − 1) one-to two-dimensional mappings. Hence, only the one-to two-dimensional shuffling algorithm is needed to realise a practical prime-factor DFT. Recently, it was shown that a new algorithm can be developed to perform the shuffling operations needed in implement the above-mentioned one-to two-dimensional mapping for a prime-factor DFT. In the paper, the new shuffling algorithm is established and proved for the general case. It is evident that this algorithm can be applied directly to many different implementations of the prime-factor DFT, including a pipeline VLSI implementation.
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