Testing of interconnection circuits in wafer-scale arrays
作者:
Y.-H.Choi,
期刊:
IEE Proceedings G (Circuits, Devices and Systems)
(IET Available online 1990)
卷期:
Volume 137,
issue 6
页码: 482-488
年代: 1990
DOI:10.1049/ip-g-2.1990.0075
出版商: IEE
数据来源: IET
摘要:
An efficient testing algorithm for interconnection circuits, including programmable switches and data links in wafer-scale reconfigurable arrays, is presented. Faulty programmable switches or data links are eliminated by finding fault-free paths in the switch grid obtained by isolating all computing units from the rest of a reconfigurable array. No internal test points are assumed. The algorithm is shown to achieve very high performance, even if cell yield is low.
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