The planarization of SiO2interlevel dielectric layers by electron cyclotron resonance reactors has been modeled as the outcome of simultaneous sputter etching and plasma‐enhanced chemical vapor deposition. This combination of etching and deposition has been simulated by the repeated sequential execution of two third‐party topography evolution codes, one for each process. The simulations reproduced observed profiles and gap‐filling properties for etch/deposition ratios from 0.45 to 0.30 and also illustrated the origin of cracks in certain nonideal gaps. The influence of the width and separation of the metal lines over which deposition was simulated was also reproduced.