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Wafer‐scale integration implementation of mesh‐connected multiprocessor systems

 

作者: Issei Numata,   Susumu Horiguchi,  

 

期刊: Systems and Computers in Japan  (WILEY Available online 1995)
卷期: Volume 26, issue 1  

页码: 1-10

 

ISSN:0882-1666

 

年代: 1995

 

DOI:10.1002/scj.4690260101

 

出版商: Wiley Subscription Services, Inc., A Wiley Company

 

关键词: WSI;Massively parallel system;Fault tolerance;Multiprocessor system

 

数据来源: WILEY

 

摘要:

AbstractWith recent advances in VLSI technology, Wafer‐Scale Integration implementation is becoming realistic, wherein massively parallel multiprocessors are implemented on a single wafer. As a result of this technique, the connections among VLSI become unnecessary and a high‐speed, high‐density system will be realized. This paper considers the mesh‐connected network, which is one of the configurations of the massively parallel multiprocessor system, and discusses the reconfiguration techniques in realizing the network on the wafer. The reconfiguration technique is necessary for composing a system on a wafer, and several techniques have been proposed to date. Most of these, however, are based on global information or can be applied only to special cases. Consequently, they are not suitable for the self‐reconfiguration scheme of a massively parallel system. From such a viewpoint, this paper proposes and evaluates an autonomic self‐reconfiguration scheme using only local information, wherein the nondeterministic algorithm is added to the conventional method. It is seen as a result that the proposed method can realize a higher yield than the conventional method, as the array size becomes larger and the portion of the redundant PE b

 

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