Experimental 1 Mbit DRAM using power reduction techniques
作者:
KatsutakaKimura,
KiyooItoh,
RyoichiHori,
JunEtoh,
YoshikiKawajiri,
期刊:
IEE Proceedings I (Solid-State and Electron Devices)
(IET Available online 1985)
卷期:
Volume 132,
issue 1
页码: 23-28
年代: 1985
DOI:10.1049/ip-i-1.1985.0006
出版商: IEE
数据来源: IET
摘要:
One of the serious problems which must be overcome in realising a 1 Mbit DRAM is high-power dissipation associated with data-line charging and discharging. To solve this problem, this paper proposes the following three techniques, which permit power reduction by about one-quarter: a multidivided data-line structure, 512 refresh cycles and an on-chip voltage limiter circuit. These techniques are proven to be useful through the design and evaluation of an experimentaln-MOS 1 Mbit DRAM with a 46 mm2chip size. The chip fabricated provides a 295 mW operating power at a 260 ns cycle time despite the fast access time of 90 ns. The possibility of further power reduction is also described.
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