1/fnoise was measured inn‐channel power transistors following high field stressing and high temperature anneals. Negative bias anneals resulted in considerably higher noise than produced by positive bias anneals. Then the bias was switched between positive and negative, the noise level switched between a low and a high level. The noise did not correlate with either interface or oxide trapped charge, but can be explained in terms of border traps and charge compensation. These mechanisms may be sufficient to explain a wide range of noise results inn‐channel metal‐oxide‐semiconductor field effect transistors. ©1995 American Institute of Physics.