As integrated circuit (IC) feature sizes shrink, correspondingly greater demands are put on the reticle writing systems for pattern placement accuracy. In raster‐scanned electron‐beam exposure systems such as MEBES which build up the pattern as a mosaic of stripes, quite small placement errors at the stripe boundaries can have serious consequences in terms of the electrical performance of the finished IC. The specifications of butting error for these exposure systems is typically 0.1 μm for a 0.25‐μm address size. While this is in itself not a serious error for most features, it can be troublesome if it shows up as a linewidth error for a submicron gate electrode. Here we have demonstrated that this error can be substantially reduced by using multiple exposures or scans to build up the pattern data so that in each exposure the stripe boundary is offset within the pattern from the remainder of the exposures. Thus, forNexposures, only 1/Nof the total dose at any one stripe boundary includes the placement error from stripe butting. Consequently, the butting error is significantly reduced in the exposed resist image. We have implemented this procedure using a novolak resist which is exposed with a scan or exposure count of 3; the reduction of the placement error by a factor better than 4 is demonstrated by metrology techniques.