New pipelined vector-reduction arithmetic unit for FIR filter implementation
作者:
Y.C.Lim,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1987)
卷期:
Volume 134,
issue 4
页码: 189-196
年代: 1987
DOI:10.1049/ip-e.1987.0034
出版商: IEE
数据来源: IET
摘要:
In realising an N-tap finite impulseresponse (FIR) filter, N multiplications and N – 1 additions must be performed during every sampling interval. The multiplication process can be pipelined easily because there is no recurrence. The (N – l)-port addition process is essentially a vector-reduction process with inherent recurrence and is a bottleneck of hardware utilisation when implemented using a pipelined arithmetic unit. In the paper we present a new pipeline structure for implementing the multiport adder. For an arithmetic pipeline with M segments, our new design achieves the theoretical upper bound on hardware utilisation provided that N ≥ (L + 2)M − 2L+1where L = Int (log2(M)), the largest integer less than or equal to log2(M). This pipeline structure is also useful in pipelined signal-processor design.
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