A scheme for selective electroless copper patterning of Si wafers has been developed with palladium silicide as the catalytic layer initiating copper deposition. Thermal conversion of a palladium layer to silicides on a SiO2patterned silicon substrate, followed by an acid etching of the unreacted palladium on the SiO2surfaces, leaves only the silicided regions at the base of the windows for electroless copper deposition. Excellent via‐filling down to 0.5‐&mgr;m dimensions and an aspect ratio of 6 has been demonstrated. The thin copper deposited on the Pd2Si has a resistivity of ∼2.0 &mgr;&OHgr; cm. Contactless photocarrier decay measurements indicate virtually no degradation of Si lifetimes by these processing steps.