This paper discusses the efficient implementation of iterative matrix operations on application specific processor arrays. Recursive equations, frequently met in a wide range of problems, can be solved through a new systolic structure, the Reconfigurable Systolic Torus, in almost optimal Area and Time requirements. Moreover, flexibility is maintained with no demand of complex instruction sets or extensive control units implemented inside the systolic cells. The general design together with the computation schedules are presented and the description of this new structure is gradually built towards the satisfaction of some basic predefined criteria.