In this paper we propose a simulation‐based algorithm, which is developed using the simulated annealing algorithm, to estimate the maximal power dissipation of sequential and combinational circuits. To trade off between the execution time and the outcomes, we use three strategies with different search spaces to generate input patterns. A statistical model is employed to analyze the equilibrium condition for each temperature in our simulated annealing process. The glitch phenomena caused by the gate delay and signal transition are also considered in this paper.