As CMOS dimensions shrink so does the limitation on total thermal budget for processing. For 0.18 μm design rules, the junction depth and the salicide process requirements limit the maximum processing temperature to below 700°C, preferably down to 650°C. For FeRAMs, this results in limitation on the thermal budget available for the crystallization of ferroelectric films. SBT and SBTN films have been generally annealed at 700°C or higher. Lowering the crystallization temperature down to 650°C requires the suppression of fluorite phase in order to obtain good ferroelectric performance. We have developed a CSD based low temperature process for SBT films yielding excellent ferroelectric properties. Several materials and process parameters have been optimized to suppress the fluorite phase. These include film stoichiometry and thickness, anneal ambient and ramp rates, UV energy and precursor solvents. In this paper we present a complete 650°C process for SBT thin films, highlighting process modifications and their effect on ferroelectric performance.