By monitoring device electrical parameters during remote plasma dry etching, we have demonstrated a novel method forinsituadjustment of saturation currents. Time‐elapsedI‐Vcurves and current‐versus‐time plots illustrate the low damage, controllable gate recess etching of a metal‐semiconductor field‐effect transistor device structure and two different high electron mobility transistors. Using a one‐dimensional Poisson solver, simulations of conduction versus depth are made and discussed in relation to experimental results.