The evolution of planar, conventional CMOS to non‐classical CMOS devices as described in the International Technology Roadmap for Semiconductors (ITRS) is discussed. The benefits of strained silicon configurations to enhance the channel mobility, silicon‐on‐insulator (SOI) to enhance the reduction of residual parasitics and non‐planar transistor device structures to improve control of the short‐channel effects are discussed. The combination of the above enhancements, in conjunction with the current state‐of‐the art global efforts in high‐k gate dielectrics, metal electrodes and elevated source/drain, offers a plethora of opportunities requiring careful assessment of the optimal solution for each organization’s portfolio of products and projected market position. Several of these possible solutions for the “ultimate” CMOS device are discussed from today’s perspective, with attention to the characterization and metrology for assessing these alternate device structures. © 2003 American Institute of Physics