Recently there is a trend for the designer to group registers into register files for efficiently implementing large VLSI chips. Multiport memories provide an effective way for such an implementation and are used in the design of many recent high-speed RISC and Superscalar processors. An efficient design methodology for datapath synthesis using onchip multiport memories is presented which can be applied to scheduled algorithms to reduce the design space. Based on simple and clear, but powerful principles, the proposed technique not only groups variables into a minimum number of multiport memories depending on their ports and access requirements of variables, but also minimises their interconnection hardware (such as buses, multiplexers and tristate buffers) to functional units. The system (memory allocator package) supports the synthesis of architecture in both linear topology and random topology for the application specific designs. The minimisation problems have been formulated as 0–1 integer linear programming problems. Experiments on benchmarks show promising results.