Parallel DFT computation on bit-serial systolic processor arrays
作者:
K.J.Jones,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1993)
卷期:
Volume 140,
issue 1
页码: 10-18
年代: 1993
DOI:10.1049/ip-e.1993.0002
出版商: IEE
数据来源: IET
摘要:
The paper shows how novel one-dimensional and two-dimensional systolic processing architectures, comprising up toNcoordinate rotation digital computer (CORDIC) processing elements (PEs), can be used to carry out hardware-efficient parallel implementations of theN-point discrete Fourier transform (DFT), offering highly attractive throughput rates in relation to the conventionalN-processor linear systolic array. The CORDIC PE is implemented in bit-serial form using single-bit half-adder (HA) and full-adder (FA) circuits. It is thus extremely efficient, in terms of speed/area product and possesses simple interconnects, facilitating the mapping of potentially thousands of such units onto a single chip.
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