A yield model is developed to estimate yield values for the serial superchip. The superchip is a large silicon chip containing many processing elements together with a communication network. Owing to its large area, the superchip concept will not be economically viable if current silicon processing technology and conventional non-redundant VLSI design techniques are employed to implement it. This paper demonstrates the result of yield improvement by employing hardware redundancy. Cost-effectiveness is also measured by the optimality of the employed redundancies.