Fault simulation in CMOS VLSI circuits
作者:
M.E.Zaghloul,
D.Gobovic,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1991)
卷期:
Volume 138,
issue 4
页码: 203-212
年代: 1991
DOI:10.1049/ip-e.1991.0027
出版商: IEE
数据来源: IET
摘要:
In digital complementary metal-oxide semiconductor (CMOS) very large-scale integration (VLSI) circuits, physical faults such as transistor stuck-closed, floating line faults, and bridging faults (which include gate-to-drain shorts) cause complex analogue behaviour of the digital circuit. Some of these faults create an intermediate voltage level, which classical switch-level fault simulator techniques are unable to interpret. A general fault simulator is proposed which employs a new technique for evaluating the faulty subcircuit based on analysis of a nonlinear resistive circuit. The technique can be considered an extension of classical switch-level level fault simulators, in which most of the possible physical faults are considered.
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