A 1200 Vn-channel insulated gate transistor (IGT) has been designed and evaluated. To reduce the Miller capacitive coupling of the input and the output terminals during the transient conditions, the terraced gate design has been implemented. As a result, the Miller capacitance is lowered 4–5 times compared to conventional gate design. Also, the gate pad is placed at the centre of the pellet so that the intrinsic device turnon and turnoff times can be shorter. To prevent current crowding and thermal fatigue around a single emitter pad, a multiple emitter pad design scheme is adopted. The 1200 Vn-IGTs have reached up to 114 A latch-up current at 150°C.