A simple expression for the inverse subthreshold slope in polycrystalline silicon thin‐film transistors (TFTs) is derived as a function of the gate voltage and with parameters the trapping states at the grain boundaries, the grain size, and the gate oxide. Comparison with the experimental results verifies the validity of the derived expression. We show that in polysilicon TFTs, even with high trapping states density and small grain size, excellent subthreshold characteristics can be obtained by scaling down the SiO2thickness to 10 nm. Further improvement in the subthreshold characteristics can be achieved using as gate oxide a Si3N4/SiO2bilayer of thickness 10 nm which has higher dielectric constant, exhibits good interface properties with polysilicon and serves as a diffusion barrier to avoid penetration effects of impurities through the oxide. ©1995 American Institute of Physics.