Radix-4 modules for high-performance bit-serial computation
作者:
S.G.Smith,
P.B.Denyer,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1987)
卷期:
Volume 134,
issue 6
页码: 271-276
年代: 1987
DOI:10.1049/ip-e.1987.0046
出版商: IEE
数据来源: IET
摘要:
We describe a technique to double the throughput of bit-serial computational networks, while retaining the many advantages associated with this architectural approach. In essence this technique relies on a 2-wire radix-4 representation of serial data: a step towards bit parallelism. As the cost of data storage associated with bit-serial architectures is not increased by this technique, it has a favourable effect on overall area-time product. Novel use of the well-known modified-Booth recoding multiplication algorithm results in further area savings. A set of functional building blocks and interfacing conventions is outlined, forming the basis of a cell library for use in a silicon compilation environment.
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