The speed of operation of a parallel adder tends to be limited by the time taken to propagate a ‘carry’ from one end to the other. Three methods have been used to reduce this limitation: special circuits, improved logic, in which carries are not propagated entirely serially, and detection of the end of carry propagation instead of waiting the maximum time.The existing literature is based either on particular transistor logic units, or on units with somewhat artificial properties. The paper considers some existing designs and some new refinements, and gives circuits for constructing them with crossed-film cryotrons. Comparisons are then made of the speed and cost of the various designs.A design of cryotron adder which is often described consists of a long ladder network. The propagation of carries in this network is found to be extremely slow. This result may be useful in guiding the design of other cryotron applications, such as special stores. The experimental analogue described in the paper and used to obtain exact speeds for a complicated network may have other applications in cryotron circuit design.