This paper discusses carrier diffusion‐induced problems that occur in profiling certain silicon structures with the spreading resistance technique. Such structures includep‐ andn‐wells, lightly doped epitaxial layers and very thin epitaxial or diffused layers. Various methods for resolving carrier diffusion problems are discussed. A new method, which we call SRP2, is introduced. In the SRP2 process, the Poisson equation is used to calculate a spreading resistance profile from an assumed dopant profile (usually deduced from conventional spreading resistance analysis or generated by a process simulator such assupremorpredict); the calculated spreading resistance profile is then compared to a measured profile to ‘‘proof‐test’’ the assumed dopant profile. Examples of the SRP2 process will be shown for CMOSp‐ andn‐wells and for several other layers, including thin epitaxial and very shallow source‐drain layers. The limits of Poisson‐based analysis for ultra‐shallow layers will be discussed.