Fault-tolerant serial-parallel multiplier
作者:
L.G.Chen,
T.H.Chen,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1991)
卷期:
Volume 138,
issue 4
页码: 276-280
年代: 1991
DOI:10.1049/ip-e.1991.0036
出版商: IEE
数据来源: IET
摘要:
The paper presents a novel fault-tolerant circuit design using a time-redundancy method for a serial-parallel multiplier, which is useful in DSP applications with serial data transmission. It utilises the RECO (REcomputing with Circularly shifted Operands) technique to detect errors concurrently. A simple OR-gate based circuit is used as the location table to identify faulty bit-slice pairs. The reconfiguration technique is then introduced to bypass the potential faulty bit-slices. This design can have the maximum detectable error region ( n/2 bits), without appending extra computing elements. The latency from error detection to location is only about two clock cycles, i.e. almost real-time detecting can be achieved. Pipe-lined timing for two computations is illustrated. The analyses of performance and complexity are described. The results show that this is an efficient design methodology for fault-tolerant multiplication with serial data.
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