AbstractThis paper describes an experimental mixed‐mode simulation system which couples an incremental time analogue simulator to an event‐driven switch level simulator. the analogue timing programme uses a variable‐step‐size, multi‐order (VSMO) numerical integration algorithm which detects and uses latency while maintaining wave‐form synchronization. the switch level programme uses piecewise linear wave‐forms rather than discrete states to model the operation of logical networks. A unified format in which time responses are events is used for communication between the two programmes. the mixed‐mode simulator operates without backtracking or translation between logical states and anal