AbstractThe present paper describes the design and prototype construction of a serial charge redistribution logarithmic A/D converter (LADC). the LADC uses only two capacitors and has an eight‐bit digital word. It directly converts the input to logarithmic code and is suitable for use with digital systems implementing the sign‐log number system. the conversion is completed in 128 steps (clock cycles). the input dynamic range is four decades and the relative error is 3.7 per cent. A capacitor ratio accuracy of 0.4 per cent is required to keep conversion errors within 1