首页   按字顺浏览 期刊浏览 卷期浏览 Characterisation and modelling of SIPOS on silicon high-voltage devices
Characterisation and modelling of SIPOS on silicon high-voltage devices

 

作者: J.N.Sandoe,   J.R.Hughes,   J.A.G.Slatter,  

 

期刊: IEE Proceedings I (Solid-State and Electron Devices)  (IET Available online 1985)
卷期: Volume 132, issue 6  

页码: 281-284

 

年代: 1985

 

DOI:10.1049/ip-i-1.1985.0063

 

出版商: IEE

 

数据来源: IET

 

摘要:

The paper describes the way a semiconducting coating, such as SIPOS, controls the spread of the depletion region near the surface of simple planar high-voltage diodes. This is important to achieve the optimum breakdown performance for high-voltage devices. When an insulating oxide separates the SIPOS from the silicon, the surface layer acts as a resistive field plate and spreads a thin depletion region right across the surface at only a few volts reverse bias. Without the oxide, or if it is thin enough to be effectively transparent to electrons and holes, the depletion region spread in the surface is limited by current flow across the SIPOS silicon interface, and the depletion spread with bias becomes more like that expected for bulk silicon. For reverse biased planar diodes, with SIPOS directly over the junction, the leakage current is proportional to the voltage to the power of 0.7–0.8 when measured at temperatures where the current through the SIPOS dominates. These effects can be modelled, neglecting any effect from thep–njunction, using lateral and vertical SIPOS-silicon interface current measurement data.

 

点击下载:  PDF (419KB)



返 回