A resistance deep level transient spectroscopy (DLTS) model is presented which shows how the surface electron traps in GaAs metal‐semiconductor field‐effect transistors may result in the extensively reported signals attributed to hole trapping at the channel and substrate interface. By considering the detailed electron capture and emission processes of the surface states, the following have been successfully explained for the strong dependence of the surface state DLTS peak height on the device geometry and temperature: (i) the device geometry dependence of DLTS peak height is found to result from the fact that the amount of surface states involved in electron capture and emission in a DLTS study is proportional to the dimension of the ungated region; (ii) the drastic decrease of surface state DLTS peak height with decreased temperature is shown to be a direct result of the strong temperature dependence of the surface leakage current; and (iii) it is shown that the ‘‘holelike’’ DLTS signals can be used directly to determine the surface electron trap energy levelET.