The Instruction Set Processor (ISP) notation was originally developed as a means of describing formally the behavioural aspects of computer systems. ISPS is a computer language based on this notation, and for which a compiler and simulator have been produced. An ISPS description of the MU5 computer has been written, verified, and used in a series of evaluation experiments conducted at Carnegie-Mellon University (CMU), Pittsburgh, from Manchester University, England, using the ARPA network. The paper presents the important features of the MU5 instruction set and introduces the notation used in ISPS through the essential features of the ISPS description of MU5. Results of benchmark programs run on the ISPS simulation model of MU5 are related to actual results obtained by hardware monitoring of the MU5 processor, and some new MU5 performance figures are given. Results are also presented for the CMU Computer Family Architecture (CFA) project test programs, and some comment is included on the validity of this type of architectural evaluation.