Novel cell architecture for bit level systolic arrays multiplication
作者:
D.Ait-Boudaoud,
M.K.Ibrahim,
B.R.Hayes-Gill,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1991)
卷期:
Volume 138,
issue 1
页码: 21-26
年代: 1991
DOI:10.1049/ip-e.1991.0003
出版商: IEE
数据来源: IET
摘要:
A novel cell architecture for bit level systolic array multiplication is presented. It is used for the design of a serial-parallel and an iterative pipelined multiplier. The new architecture is a result of combining, in a novel way, the operation of two gated full-adder cell used in conventional multipliers. The new cell circumvents the insertion of zeros in structures with contraflow data streams. As a result, the array is used with 100% efficiency, and the throughput rate is doubled in comparison to most systolic arrays using the contraflowing approach. This is achieved without any increase in hardware, nor the use of a special clock circuitry. Performance analysis of the new multipliers and existing ones has shown the superiority of the new architecture.
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