This paper presents an analytical moderate inversion drain current model for polycrystalline silicon thin‐film transistors based on localized deep and tail states in the grain boundary regions. As verified by the published data, using the analytical model, that as compared to the subthreshold region in the bulk iliccon metal‐oxide‐silicon (MOS) devices, the less steep slope of the moderate inversion region has been explained as due to the lowering in the potential barrier height. In addition, the analytical model provides an accurate prediction that with a smaller average trap state density from the grain boundary regions, the polysilicon thin‐film transistor shows a sharper moderate inversion behavior. ©1996 American Institute of Physics.