The logic cellular array of a division device that is based on the SRT division algorithm extended to the case of redundant representation of the partial remainders is reported. In the paper, redundant binary representation of the partial remainders is due to the fact that any digit can have the following values: minus one (1), zero (0) and plus one (1). Comparison of the logic array proposed with other cellular logic arrays reported in the literature for binary division yielded that, with the former design, greater operating speeds may be attained.