An electron‐beam‐lithography‐compatible process for the fabrication of depletion mode and accumulation mode insulated gate field effect transisitors on InP has been developed and is reported in detail. The exposure system uses an unmodified scanning electron microscope interfaced with a minicomputer. Transistor gate length dimensions for the completed devices range from several microns to submicron, and the smallest gate length for the depletion mode device measures 0.25 μm. Device operation is presented and discussed, and device performance is shown to compare well with long gate devices made by optical lithography.