AbstractFor economic raster graphics equipment capable of the display of high resolution dynamic pictures of 3‐D solids, 3‐D wire frames, and 2‐D wire frames ‐ in decreasing order of stringency, the design of the pixel memory system is a key issue, due to the high pixel writing speeds required. This paper discusses some new architectural possibilities for such a memory system.To give some idea of problem scale, present investigations indicate that pixel generation rates from an economic tiling circuit of up to 25 Mhz may be possible ‐ 40 ns per pixel. However, using contemporary dynamic RAM'S memory read‐modify‐write cycle, including computation on the data read from the memory (for example masking in the new pixel data or z‐depth‐buffer arithmetic) may take 400 ns i.e. a speed difference of about 10:l exists.The matching of these differing data rates demands a departure from traditional pixel memory architecture. Here a possible philosophy of approach is discussed together with the results of a simulation study. The proposed architecture is able to keep costs, bulk and power consumption down by using cheap, industry standard, high density memory components. Its use is additionally shown to be compatible with the generation of dynamic views of bolids using dep