Systematic procedure for test generation of PAL-based circuits
作者:
P.K.Lala,
S.Shen,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1989)
卷期:
Volume 136,
issue 2
页码: 142-149
年代: 1989
DOI:10.1049/ip-e.1989.0019
出版商: IEE
数据来源: IET
摘要:
Programmable array logic (PAL) devices can be used for realising both combinational and sequential circuits. The final behaviour of a PAL chip is determined by the fuse pattern in this chip. This paper presents a systematic procedure for generating a minimal test set to examine whether a programmed chip functions as expected. The upper bound of the size of a test set generated by the proposed procedure is also derived.
点击下载:
PDF
(841KB)
返 回