A process technique to integrate the sputter-deposited BST thin film into the DRAM is discussed. With some reconsiderations concerning the grain structure of the BST, the care of the electrode edge, the thermal stability of the capacitor characteristic, the upper dielectric of the capacitor and so on, the BST was successfully integrated into a capacitor TEG structure on a 9Mbits scale. By using the newly developed integration technique, a 4MDRAM was fabricated, exhibiting the normal bit function with a wide margin. After this, improvements on the thermal stability are needed by developing a barrier layer under the bottom Pt electrode that is more heat-resistant than currently achieved.