The generation of slip dislocations in BF2ion‐implanted, 100‐mm‐diam silicon wafers during rapid thermal annealing is investigated. Whole wafer x‐ray topography shows that annealing at 1150 °C causes slip to initiate randomly at positions of maximum resolved stress at the wafer edges and over scribe marks made on the back surface prior to annealing. Lowering the annealing temperature by 20 °C, which corresponds to decreasing the silicon yield stress by less than 106dyn cm−2, prevents slip from occurring and allows sufficient removal of implantation‐induced defects from which junction diodes with good current‐voltage characteristics are fabricated.