A novel technique for a gated silicon field emission cathode is proposed in order to decrease the spacing between the tip and the gate electrode of the device, which leads to low voltage operation. This technique is based on the filling characteristics of the sputteredTi0.1W0.9layer, which is used as the gate electrode in the shadowed area surrounding the tip with good step coverage. This process is completely compatible to conventional 1.2 μm complementary metal–oxide–semiconductor standard processes. The experimental results indicate that the diameter of the gate hole is greatly reduced to a subhalf-micron dimension(∼0.4 μm)even when starting with an initial mask size of 1.2 μm. TheI–Vcharacteristics of the cathodes show low turn-on voltages(∼25 V)in high vacuum(<3.0×10−7 Torr).The Fowler–Nordheim plots also show good linearity.