摘要:

The design and implementation of SJ16, a 16-bit microprogrammable processor chip, is presented. Novel features include a newregenerativecarry scheme, a systolic stack control mechanism, and microprogram sequencing based upon the microAPL high-level microprogramming methodology. Relevant CMOS design issues are discussed.

DOI:10.1049/ip-e.1988.0011

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Previous solutions to the problem of synchronising fault-tolerant multiprocessor systems require either 3t+1 processors (fort-fault- tolerance) or else multiple rounds of messages with unforgeable digital signatures. These solutions are too expensive for small microprocessor-style control systems. The paper shows that simple constraints on the physical design of the communication links permit a much more economical solution with just 2t+1 processors and one round of messages, without the need for unforgeable signatures.

DOI:10.1049/ip-e.1988.0012

出版商:IEE    

年代:1988

数据来源: IET

摘要:

An in-depth study of RESO (recomputing with shifted operands) theory is conducted which leads to the extension of the theory so that efficient CED designs for two-dimensional array structures and complex functions can be achieved. Based on the enhanced version of RESO, a systematic design strategy has been developed to allow the designer to take advantage of knowledge of fault configurations.

DOI:10.1049/ip-e.1988.0013

出版商:IEE    

年代:1988

数据来源: IET

摘要:

A new method of compression, called sequential block interleave coding (SBIC), is presented which features a fixed-rate output and exhibits a strong immunity to transmission errors. The method encodes block-pairs of binary image data over a field of blocks without the need for codebooks. By initially scrambling blocks the field size requirement can be considerably decreased, thereby reducing the propagation effect of transmission errors. In its lossless form the implementation is quite straightforward, requiring primarily storage operations and simple identification of block-pair states. For better noise immunity, a lossy form of coding is preferred with encoding distortion taking the form of lost black elements. For the set of test images employed, the results of simulation have shown that it is possible to obtain a bit rate reduction of 38% (CR = 1.6) using 8-pel blocks, while good intelligibility can be maintained in the decoded image in the presence of transmission errors whose average error rate may be as high as one in 32 bits. Additional compression may be obtained by cascading the SBIC technique with block-to-block coding (giving 50% bit rate reduction for the test images), at the expense of increased sensitivity to transmission errors.

DOI:10.1049/ip-e.1988.0014

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Generalised Boolean functions are useful in the design of programmable logic arrays. In this paper a heuristic algorithm suitable to minimise such functions is presented. The algorithm generates an irredundant cover by using a local approach to select generalised prime implicants. A benefit of such a method is that the preliminary generation of the set of all the generalised prime implicants is not required. Experimental results are presented, showing a favourable comparison with an already established minimisation algorithm as far as computing speed is concerned.

DOI:10.1049/ip-e.1988.0015

出版商:IEE    

年代:1988

数据来源: IET