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| 1. |
Virtual resource ring: Technique for decentralised resource management in fault-tolerant distributed computer systems |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 2,
1984,
Page 38-44
R.Hull,
F.Halsall,
R.L.Grimsdale,
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摘要:
The paper first identifies design objectives for resource management in distributed computer systems. A resource-management mechanism that meets these objectives, the virtual resource ring (VRR), is then proposed and an implementation of the VRR on an actual distributed multiprocessor computer system is described. Finally, the proposed scheme is evaluated against the previously defined design objectives.
DOI:10.1049/ip-e.1984.0007
出版商:IEE
年代:1984
数据来源: IET
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| 2. |
Performance measurements of scheduling strategies and parallel algorithms for a multiprocessor quick sort |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 2,
1984,
Page 45-54
J.Chen,
E.L.Dagless,
Y.Guo,
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PDF (1253KB)
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摘要:
A variety of parallel algorithms running under a contention scheduler and a master/slave scheduler and implemented on the CYBA-M multiprocessor are described and a new predistributed quick sort is reported. Results show speed up factors of 7.88 for 13 processors, and processor utilisations greater than 75% for 10 or more processors are predicted when sorting large lists with long keys.
DOI:10.1049/ip-e.1984.0008
出版商:IEE
年代:1984
数据来源: IET
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| 3. |
Combined resource-sharing algorithm |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 2,
1984,
Page 55-60
I.A.Newman,
R.P.Stallard,
M.C.Woodward,
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PDF (846KB)
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摘要:
The increasing use of multiprocessor systems in a variety of circumstances has highlighted a requirement for improved co-ordination algorithms for those systems where communication is via data structures in shared memory. In this paper, two classes of algorithm are described, and their principal characteristics are discussed. A hybrid algorithm having the advantages of both classes is then proposed. Finally, figures giving the performance of this algorithm on a four-processor shared-memory system are compared with those for alternative algorithms.
DOI:10.1049/ip-e.1984.0009
出版商:IEE
年代:1984
数据来源: IET
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| 4. |
Memory interference in multimicroprocessor systems with a time-shared bus |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 2,
1984,
Page 61-68
P.A.Grasso,
T.S.Dillon,
K.E.Forward,
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PDF (952KB)
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摘要:
Two mathematical models are presented for the analysis of memory interference in time-shared-bus multimicroprocessor systems. The first is a discrete-time queuing model and the second is a Markov model. The measure of performance in each case is the fractional increase in execution time resulting from bus contention. Another measure, which is derived from this, is the speed up of the multiprocessor as compared to a uniprocessor. These models are tailored to suit the requirements of real-time microprocessor systems and thus are different from much of the literature on memory interference which is directed toward general-purpose multiprocessor systems. The validity of the models is verified by comparison with simulation results and actual hardware measurements.
DOI:10.1049/ip-e.1984.0010
出版商:IEE
年代:1984
数据来源: IET
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