摘要:

The minimum-time control of robot arms has usually been implemented as a two-task procedure, where the appropriate trajectory planning is performed off-line, and then tracking is carried out on-line to achieve the desired motion. However, such an approach is unacceptable whenever the motion is dependent on the on-board sensory equipment operated during the application. In the paper, an on-line trajectory generator is described in which the history of motion is planned and executed in real time. The computational complexities of the minimum-time requirements of the motion have been reduced significantly by distributing the proposed algorithm on a multiprocessor system. The practical implementation of the distributed system on a T800 transputer network shows its efficiency in accomplishing the required task. Real-time simulation results are reported for a PUMA 560 robot manipulator.

DOI:10.1049/ip-e.1991.0023

出版商:IEE    

年代:1991

数据来源: IET

摘要:

A new pipelined systolic design for residue error correction using Chinese remainder theorem is described which has a higher throughput compared with previous methods and minimum time latency. In addition, the new design has the capability of overflow detection and self-diagnosing.

DOI:10.1049/ip-e.1991.0024

出版商:IEE    

年代:1991

数据来源: IET

摘要:

A survey of the state of the art in learning systems (automata and neural networks) which are of increasing importance in both theory and practice is presented. Learning systems are a response to engineering design problems arising from nonlinearities and uncertainty. Definitions and properties of learning systems are detailed. An analysis of the reinforcement schemes which are the heart of learning systems is given. Some results related to the asymptotic properties of the learning automata are presented as well as the learning systems models, and at the same time the controller (optimiser) and the controlled process (criterion to be optimised). Two learning schemes for neural networks synthesis are presented. Several applications of learning systems are also described.

DOI:10.1049/ip-e.1991.0025

出版商:IEE    

年代:1991

数据来源: IET

摘要:

The paper introduces the generalised hierarchical massively parallel system (MPS) and extends data transfer parallelism to all members of the memory hierarchy. Methods are presented for connecting multiple parallel disks and parallel memory modules to the generalised hierarchical MPS. Full utilisation of data transfer bandwidth between disks and processing elements is facilitated by structuring and corner turning the incoming data before storing it on parallel disks. One major application of MPSs is image processing. The methods presented perform well on image data. The total system is generalised by introducing architectural parameters. Varying these parameters allows the system to be represented as various forms of SIMD architecture. A new SIMD massively parallel system, BLITZEN, is used as an example to illustrate some of the concepts presented.

DOI:10.1049/ip-e.1991.0026

出版商:IEE    

年代:1991

数据来源: IET

摘要:

In digital complementary metal-oxide semiconductor (CMOS) very large-scale integration (VLSI) circuits, physical faults such as transistor stuck-closed, floating line faults, and bridging faults (which include gate-to-drain shorts) cause complex analogue behaviour of the digital circuit. Some of these faults create an intermediate voltage level, which classical switch-level fault simulator techniques are unable to interpret. A general fault simulator is proposed which employs a new technique for evaluating the faulty subcircuit based on analysis of a nonlinear resistive circuit. The technique can be considered an extension of classical switch-level level fault simulators, in which most of the possible physical faults are considered.

DOI:10.1049/ip-e.1991.0027

出版商:IEE    

年代:1991

数据来源: IET

摘要:

A useful theoretical model for the transfer of data inside a hypercube multiprocessing network is developed. This model defines a statistical parameter λ which can be interpreted both as an average distance travelled by data within the network and as a measurement of how much memory sharing occurs within the network during the execution of a program. A simple model for the node in a distributed memory hypercube is derived to show data flow. Methods of estimating the time required for data transfer are also developed. A simulation for the data flow model is included.

DOI:10.1049/ip-e.1991.0028

出版商:IEE    

年代:1991

数据来源: IET

摘要:

Two classes of systolic architectures are presented that are able to compute bicubical B spline or Bezier polynomial coefficients and carry out polynomial evaluations. Using a pair of full arrays it is possible to compute all the coefficients in parallel, and to evaluate the polynomials for a given surface, as well as provide a speedup factor of more than 1500 compared with the single processor computation. An alternative solution is to partition both tasks into smaller sub-tasks so that a reduced size of the array is required. This allows a reasonable tradeoff between the speed needs and the VLSI implementation requirements to be achieved.

DOI:10.1049/ip-e.1991.0029

出版商:IEE    

年代:1991

数据来源: IET

摘要:

The problems of designing microprocessors using a silicon compiler are discussed. The example used throughout the paper is the Motorola MC6800. Details are given as to how the software description of the microprocessor was developed and optimised, how it was tested, and the necessary modifications required for the silicon compiler used. Consideration is given to faster, parallel architectures which give significant speed improvements at the cost of an increase in complexity.

DOI:10.1049/ip-e.1991.0030

出版商:IEE    

年代:1991

数据来源: IET

摘要:

The use of a simple hybrid cellular automaton (combining rules 90 and 150 in Wolfram's notation) as a built-in self test (BIST) structure for VLSI systems is considered. Two six-bit pseudorandom number generators based on cellular automata (CA) and LFSR have been designed using 2μm design rules for an N-well CMOS process. Layout has been achieved using ChipWise. Comparative performance studies of these CA-based new pseudorandom number generators and the LFSR-based generators show the great advantage of these CA-based BIST structures over the LFSR. The group and semigroup algebraic properties of 1-D null bounded elementary cellular automata with the linear evolution rules 90 and 150 are also presented and discussed, together with their state transition graphs. The variety of symmetries of these CA systems results in a multiplicity of functional dependences for the group and semigroup orders of the associated algebraic structures and the CA length N.

DOI:10.1049/ip-e.1991.0031

出版商:IEE    

年代:1991

数据来源: IET

摘要:

This paper deals with the automatic geometrical testing of three-dimensional objects from profile range images. This involves a scheme for automatically aligning, comparing and best fitting profile range images of a component with a corresponding model. Profile range images are directly obtained using range finding equipment. After an alignment process, these are then compared with mathematical models of the component generated in a computer aided design (CAD) system by emanating normals from the model and determining where they intersect the image surface. A Gaussian least square best fit of the model to the measured component is then computed to two degrees of freedom which takes the overall surface differences into account. Surface differences are expressed by two translation terms. This method can be extended to a maximum of six degrees of freedom.

DOI:10.1049/ip-e.1991.0032

出版商:IEE    

年代:1991

数据来源: IET