摘要:

The paper introduces a criterion for test generation based on minimising the expected magnitude of undetected errors. This criterion is used to develop a best strategy for testing, using the linear checks approach. The detailed analysis is carried out for single unidirectional and bidirectional errors and for multiple unidirectional errors. Specific results concerning the efficiency of the approach are given for basic arithmetical and logical instructions. This approach may be useful in the field testing of hardware which carries out data manipulation and in which small numerical errors can be tolerated; it may also be useful for testing digital transmission channels.

DOI:10.1049/ip-e.1982.0035

出版商:IEE    

年代:1982

数据来源: IET

摘要:

Demand-assigned multiple-access (DAMA) schemes in which requests for communication channels are transmitted over shared collision-type channels to a master controller, and in which messages of different priorities are present, are analysed. Priority use of the request channels is achieved by having users select among those channels according to a priority-dependent probability distribution. Two important schemes of this class are considered. Additionally, three schemes for priority assignment of message channels are treated: two are non-pre-emptive and one is pre-emptive. Trade-offs among bandwidth utilisation and delay are considered, as well as optimisation of system parameters.

DOI:10.1049/ip-e.1982.0036

出版商:IEE    

年代:1982

数据来源: IET

摘要:

A variant of the substitution-permutation encryption network, which incorporates random permutations, is presented and shown to retain, with a very high probability, the cryptographically important property of completeness after a small number of rounds. Although the increase in crypto-cost is moderate, the advantage of the new variant is twofold, in that a proof for the freedom from an intentional trapdoor is provided and the network can offer a higher level of cryptosecurity.

DOI:10.1049/ip-e.1982.0037

出版商:IEE    

年代:1982

数据来源: IET

摘要:

By using multiple processors it is possible to increase the computing power and hence the complexity of the task that can be managed by a microprocessor-based system. To be useful, such a system must consist of (a) hardware, (b) development software, which provides program development support, and (c) operating-system software which executes on the multiprocessor and provides run-time support for applications programs. In this paper, we present the design of an operating system intended for dedicated real-time multiprocessor applications. The problems encountered in designing such a system are discussed, together with the solutions which we have adopted. The use of our system for parallel processing is illustrated by two example applications.

DOI:10.1049/ip-e.1982.0038

出版商:IEE    

年代:1982

数据来源: IET

摘要:

The paper is an exposition of some of the design principles involved in the development of a dynamically reconfigurable vector-slice processor. Implementable in terms of commercially available VLSI components, the reconfigurable processor is designed to meet the requirements of the numerical user who can avail himself of a tradeoff between parallel activity and numerical accuracy. To this end, the processing heart of the system can be dynamically altered by the user to enter one of a number of predefined configuration states, each one of which represents an altered level of parallelism balanced against the width of each parallel subprocessor in the configuration. The paper describes, in some detail, the structure of the processor in terms of both its control and data paths.

DOI:10.1049/ip-e.1982.0039

出版商:IEE    

年代:1982

数据来源: IET