摘要:

The effect of structure on microprocessor-based recursive digital filters which employ a predetermined multiplication technique based on the canonic signed-digit code is considered. It is shown that, by including structure as a parameter in the design of such filters, transfer-function coefficient quantisation error may be reduced. A set of design rules for choosing the best structure to implement a 2nd-order transfer function, which has pairs of zeros located at + 1 or − 1 in the complexz-plane, is developed. These rules are applied to an 8th-order Chebyshev type bandpass filter, realised as a cascade of four 2nd-order sections by a microprocessor designed specifically for signal processing.

DOI:10.1049/ip-e.1983.0008

出版商:IEE    

年代:1983

数据来源: IET

摘要:

The paper describes the implementation and design of an adaptive digital filter. A brief introduction to the theory of adaptive filtering is first undertaken; this is followed by a description of the hardware used in the implementation. At this point, finite wordlength considerations are outlined. A consequence of these finite wordlength constraints – namely deadspace in the adaptive update equations – is investigated and a new method for reducing this deadspace, by use of an additive dither signal in the weight vector update algorithm, is proposed. Simulation results which confirm the utility of the method are included. Experimental results obtained from the hardware described are presented. A technique for determining required wordlength for digitally implemented adaptive filters is outlined. Finally, limitations of the design are discussed, along with possible applications.

DOI:10.1049/ip-e.1983.0009

出版商:IEE    

年代:1983

数据来源: IET

摘要:

Shared-bus interconnection schemes normally suffer from insufficient capacity. Increasing their bandwidth reduces the problem but makes bus arbitration somewhat difficult. This paper presents a fair bus-arbiter design, its implementation and simulation results. Although the techniques originated from the particular constraints of the architecture considered, it is generally applicable to high-speed arbitration problems and has a low hardware cost.

DOI:10.1049/ip-e.1983.0013

出版商:IEE    

年代:1983

数据来源: IET

摘要:

The performance of two synchronisation schemes is compared. One scheme uses a fixed-period clock with the allowable resolution time of the synchronising flip-flop being one clock period, the other scheme uses a clock with extensible clock-pulse recurrence time and a special flip-flop with an additional output,M, which is asserted whenever the flip-flop is in the metastable state. By asserting the PAUSE input to the clock, clock-pulse generation is inhibited. TheMoutputs of the rank of flip-flops are collectively ORed to drive the PAUSE input of the clock, thus pausing clock-pulse generation when one or more of them is in the metastable state. A system using the first scheme fails when conflicting actions are taken by its components, owing to inconsistent interpretation of the outputs of the flip-flops that are in the metastable state. In the second scheme, a system fails when the job execution time exceeds a specified upper bound, owing to extension in clock pulse recurrence times. If the path delays from theMoutputs to the PAUSE input of the pausable clock are small, the second scheme performs better. However, its performance degrades exponentially as the delays increase.

DOI:10.1049/ip-e.1983.0014

出版商:IEE    

年代:1983

数据来源: IET