摘要:

Asynchronous VLSI circuits have been proven to be more tolerant to persistent defects, such as stuck-at faults, than their clocked counterparts. However, such circuits are directly reactive to input stimuli and so they can be more vulnerable to transient faults at their inputs. The ability to tolerate such faults is most crucial for interface circuits, or transducers, which are the informational kernel of any system. For example, an unspecified signal change at some of the transducer's links can produce a harmful effect on other links and influence the behaviour of the whole system. Types of faults and specific requirements of asynchronous transducers, under the various assumptions about the correctness of their and the environment's implementation, are investigated. A structural method, based on synthesising a correct circuit for the transducer from its original specification made under the assumption that the environment is correct, and then augmenting it by a structurally separate ‘wrapping’ of a special protection logic, is proposed. This logic consists of the perfect mirror model and adjudicator components which are built separately for each of the transducer links. The discussion makes use of the formalism of trace structures and their conformance introduced by Dill. The approach appears to be most efficient when the links between the transducer and the environment utilise standard handshake protocols.

DOI:10.1049/ip-e.1993.0011

出版商:IEE    

年代:1993

数据来源: IET

摘要:

Galois field multiplication is central to coding theory. In many applications of finite fields, there is need for a multiplication algorithm which can be realised easily on VLSI chips. In the paper, what is called the Babylonian multiplication algorithm for using tables of squares is applied to the Galois fieldsGF(qm). It is shown that this multiplication method for certain Galois fields eliminates the need for the division operation of dividing by four in the original Babylonian algorithm. Also, it is found that this multiplier can be used to compute complex multiplications defined on the direct sum of two identical copies of these Galois fields.

DOI:10.1049/ip-e.1993.0012

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The problem of detecting lines in an image withNedge pixels on mesh connected computers withNprocessors is considered, and four new and efficient algorithms which detect lines by performing a Hough transform are presented. The first algorithm runs inO(N½+n) time on a 2D (2 dimensional) mesh, wherenis the number of θ values considered. The second algorithm runs inO((N/n)½+n) time on a 3D mesh. The third algorithm runs inO(log(N/n)+n) time on a mesh plus tree, and the fourth algorithm runs inO(nlogN/logn) time on a mesh with reconfigurable buses. All of the algorithms presented in the paper have smaller time complexities than the known results in the literature.

DOI:10.1049/ip-e.1993.0013

出版商:IEE    

年代:1993

数据来源: IET

摘要:

Two new processor arrays for the 2D discrete Fourier transform are proposed. Both structural schemes are oriented towards VLSI technology. They can be used in the construction of high-throughput processors for multidimensional and fast Fourier transforms as well as triple matrix mutiplication. The first structural scheme consists of two successively connected one-dimensional arrays of processor elements (PEs), and the second one represents a single array of more complex PEs. The advantages of these structural schemes are the localisation of all data exchanges between PEs and the absence of necessity of matrix transposition.

DOI:10.1049/ip-e.1993.0014

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The paper describes Reed-Muller universal logic modules (RM-ULMs) and their use for the implementation of logic functions given in Reed-Muller (RM) form. A programmed algorithm is presented for the synthesis and optimisation of RM-ULM networks. The level-by-level minimisation procedure is based on the selection of control variables at different levels with the aim of maximising the number of discontinued branches and hence minimising the number of modules required to implement a given function. The algorithm is programmed in Fortran and can be used to realise fixed-polarity generalised Reed-Muller (GRM) expansions of any polarity and any number of variables.

DOI:10.1049/ip-e.1993.0015

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The problem of describing texture colours in a concise way is analysed. This problem is formulated as a colour quantisation problem, where the texture image is quantised using the smallest numberkof representative colours given some criteria. These colours are the texture characteristic colours, and an algorithm is proposed to obtain them. It is shown that a network of simple processing elements implements a generalisation of the algorithm that outperforms it in many cases. Some applications of the proposed approach are colour texture discrimination and classification.

DOI:10.1049/ip-e.1993.0016

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The paper introduces algorithms that map single and multiple multilevel structures onto the hypercube. For the case of the pyramid, which is a special multilevel structure, it is shown that a new algorithm is a compromise among existing algorithms with regard to cost and performance. Comparative analysis of the algorithms is carried out using analytical techniques and simulation results.

DOI:10.1049/ip-e.1993.0017

出版商:IEE    

年代:1993

数据来源: IET

摘要:

There is a well established and growing need for fast digital processors and fast digital systems generally in many areas of application. In the design of sequential logic in particular, the problems of clock skew and the fact that the clock period is essentially determined by the speed of the slowest parts of the system are significant limiting factors. Consequently, attention is turning to asynchronous, self-timing, systems to provide a way of achieving extra speed in time-critical applications. Designers may well argue that asynchronous circuitry is difficult to design and prone to all sorts of hazards and potential instability problems but, on the other hand, the clock distribution layout of very fast synchronous systems is also quite difficult to design and simulate. Traditional asynchronous design methods are, in the opinion of the author, quite cumbersome and often difficult to use. Attention is therefore turning to ways of improving asynchronous circuit representation and design processes. An alternative way of approaching the representation and design of asynchronous sequential systems is to take an ‘event-driven logic (EDL)’ or ‘transition-based’ approach. In concept, the approach taken is to define the initial conditions of a system in terms of the logic level assumed by each variable and then to describe subsequent system behaviour in terms of the transitions (changes in logic level, also called events) of those variables. The paper pursues this approach, making use of special operators and introducing appropriate EDL functions and design processes.

DOI:10.1049/ip-e.1993.0018

出版商:IEE    

年代:1993

数据来源: IET

摘要:

In the paper, a new augmented binary-tree multiprocessor architecture, called LAB-tree, is proposed. It consists of ann-level full binary tree augmented with (2n−2) redundant links. The short and regular redundant links improve several properties of the full binary tree, such as increased tolerance, reduced traffic congestion and efficient routing of messages. It is shown that there exist at least two node-disjoint paths between every pair of nodes in the LAB-tree. In fact, all nonfaulty nodes remain connected in the presence of one faulty node at each level of the tree. The LAB-tree supports simple shortest-path routing algorithms which distribute messages evenly over links. The LAB-tree can be constructed modularly in VLSI by interconnecting modules of smaller size.

DOI:10.1049/ip-e.1993.0019

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The behaviour of Hubnet is studied and analysed. A simulation model is developed from which the effect of the retry time on the performance of Hubnet is studied. It is shown that there is an inherent dependency between the packet length and the retry time. According to this dependency, retry time-values which are factors of the packet length exhibit superior performance in terms of reduced average delay and increased system utilisation, even when compared with some systems with smaller retry times. A novel analysis of Hubnet under overload conditions is provided. It is shown that Hubnet, under overload conditions, operates in a round-robin fashion, and that the channel-access time is bounded. The performance of Hubnet in a prioritised environment is explored. It is shown that Hubnet is a very good candidate for voice and data integration.

DOI:10.1049/ip-e.1993.0020

出版商:IEE    

年代:1993

数据来源: IET