摘要:

The last few years have seen considerable progress in the development of techniques for producing silicon-on-insulator (SOI) substrates suitable for fabrication of high performance devices/circuits. Among the most promising of the new ideas are those based on buried dielectric formation by ion implantation (oxygen or nitrogen), recrystallisation of deposited polycrystalline silicon-on-insulator (using lasers, electron beams, hot wires, strip heaters or incoherent light), and oxidation of porous silicon. A number of other techniques also show potential. The concept of SOI is not new, however. Attempts to grow single crystal semiconductor films on insulating substrates date back almost 40 years with the first successes in the growth of silicon layers in the early 1960s. During that period epitaxial silicon-on-sapphire (SOS) emerged as a viable approach to SOI, since when it has become a well established technology for MOS with a unique role to play in some important areas of application. The new substrate types promise to extend the range of applicability still further. Indeed, some workers predict a revolution, following which, for MOS technology at least, single crystal silicon substrates will play a minor role in comparison to SOI. This paper outlines these different approaches to SOI and reviews their advantages for a number of important application areas, placing particular emphasis on MOS technology. Applications such as VLSI, memory, structured, random and high speed logic, analogue circuit design and defence electronics are considered. Recent developments in the preparation of SOI substrates have led to the successful realisation of a range of novel ‘stacked’ structures exploiting, for example, two (or more) independent layers of devices, common gates or common device channels. Progress in and the potential of this exciting new field of three-dimensional integration is reviewed also.

DOI:10.1049/ip-e.1986.0014

出版商:IEE    

年代:1986

数据来源: IET

摘要:

The paper discusses the impact of cell-based design techniques and VLSI technology. The paper considers cell-based chip design including the design tools and interfaces from logic design, through floorplanning to implementation. Finally, the advantages and limitations of cell-based design are summarised, leading to suggestions and recommendations for the next generation cell library approach.

DOI:10.1049/ip-e.1986.0015

出版商:IEE    

年代:1986

数据来源: IET

摘要:

The VLSI design process must address the fields of definition, realisation and verification of complex systems. The most important aspect is the management of the complexity in all three fields. The paper discusses the use of structures to aid in these objectives, and describes a particular process sequence. The field of VLSI design is characterised by somewhat obscure terminology. The key to understanding the operations involved in VLSI is seen as a clear definition of these terms in this context, and also their inter-relationships. The terms addressed here are: structure; function; behaviour; hierarchy; abstraction. The design process is widely regarded as being essentially a top-down process, from a precise definition of required function, progressing through a hierarchy of functional levels to the full implementation of the system. A practical situation is discussed, where a process of refinement is applied at each level and the use of structured design enables a degree of bottom-up definition to be incorporated into the design flow. The use of structures in a design introduces the need for design partition. Partition implies communication between the parts. Communication is seen as a vital aspect of system behaviour. Partition frequently is applied to the design team also, and this requires communications between designers, a further important link in the design process. The detailed interplay between definitions and descriptions, both up and down the hierarchy and also between the different design abstractions is seen as the essential activity of the design process where a structural approach is applied. The features of the design system necessary to support this activity are discussed. The status of test in the design process can never be placed too high. The significance of structured design on the ease and validation of test is therefore also considered.

DOI:10.1049/ip-e.1986.0016

出版商:IEE    

年代:1986

数据来源: IET

摘要:

Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilises simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioural description languages. These differ from inherently structural hardware description languages (HDLs) in that they not only allow behaviour and structure to be described, they also support formal behavioural analysis using mathematical techniques. Necessary features of a behavioural description language are presented and the application of this language to VLSI description, design and verification is illustrated.

DOI:10.1049/ip-e.1986.0017

出版商:IEE    

年代:1986

数据来源: IET

摘要:

Image reconstruction by computer tomography provides a nonintrusive method of imaging the internal structure of objects. From measurements of radiation (e.g. X-rays or gamma rays) passed through an object, it is possible to reconstruct the internal structure. There is great interest in the potential of such methods in industrial applications but a number of problems need to be solved before these opportunities can be realised. The reconstruction process is computationally intensive and requires imaginative parallel processing algorithms to attain ‘real-time’ performance. The work carried out has involved evaluating how these algorithms can be used in multiprocessor concurrent architectures to obtain rapid image reconstruction. A suitable computer architecture has been simulated in occam. This allows execution on a collection of transputers.

DOI:10.1049/ip-e.1986.0018

出版商:IEE    

年代:1986

数据来源: IET

摘要:

The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and logic for communication with other processing elements. Packing 143K transistors on a 73 mm2silicon die, with 2.5 μm p-well (two-layer metal) CMOS design rules, the SCAPE chip is packaged in a 68-pin chip carrier and, operating at 10 MHz, dissipates less than 900 mW. The paper describes the SCAPE chip architecture and floor plan in structural detail. Testability considerations, design verification and SCAPE software are discussed, and the results from recent performance simulation studies are also reported. The SCAPE chip is scheduled for fabrication, by Plessey (Caswell), in the second quarter of 1986.

DOI:10.1049/ip-e.1986.0019

出版商:IEE    

年代:1986

数据来源: IET

摘要:

A novel fine-grain parallel-processing microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing computational structure, the architecture provides particularly flexible support and manipulation of abstract data structures over a wide range of information processing tasks. Moreover, the architecture is well suited to the technological constraints of VLSI chip and, especially, WSI device fabrication. The paper describes the ASP (associative string processor) architecture and its instruction set. The style of associative string processing is introduced with three algorithms, illustrating both relational and arithmetic operations. Current projects leading to VLSI ASP chips and WSI ASP devices are discussed and ‘ball-park’ performance figures are given.

DOI:10.1049/ip-e.1986.0020

出版商:IEE    

年代:1986

数据来源: IET

摘要:

Logic programming provides new ways of solving problems by computer, and offers opportunities for concurrent processing. The declarative style of logic programming is contrasted with the imperative style of conventional programming languages. A simple example of a logic network is used to draw out the distinction, and is followed by a review of the corresponding execution sequence. The operations of variable binding and unification are discussed in detail. The Syracuse unification machine, a coprocessor for a logic programming system, has been designed to carry out these operations efficiently with the aid of concurrent processing units and content-addressable memory.

DOI:10.1049/ip-e.1986.0021

出版商:IEE    

年代:1986

数据来源: IET

摘要:

The testing of VLSI circuits is becoming progressively more difficult as device densities increase. This has brought about several proposals for designing VLSI circuits with testability built in. A method is presented in the paper for the design of easily testable VLSI circuits with a view to producing fault tolerant systems. A microprocessor datapath is used to illustrate the technique. The method used for checking the VLSI devices is an error detecting code, in this case a residue code. Residue codes offer several advantages over linear block codes for providing testability in a wide range of VLSI circuits. A detailed evaluation of the increase in chip area required to produce a self testing chip is also given in the paper.

DOI:10.1049/ip-e.1986.0022

出版商:IEE    

年代:1986

数据来源: IET