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1. |
Adaptive windows for image processing |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 132,
Issue 5,
1985,
Page 233-245
I.Aleksander,
M.J.Dobree Wilson,
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摘要:
Window operators for image processing are described which are trained to achieve desired transforms rather than being stated as mathematical operations. This provides the user with a great deal of freedom in choosing and optimising for specific tasks. Both the theory and some practical results are detailed in order to illustrate the relationship between the structure of alternative systems, their training and eventual performance. The creation of spatial frequency filters and edge detectors are among the examples used to illustrate the process. The nature of several implementations and their cost effectiveness in terms of memory demand is included in the discussion.
DOI:10.1049/ip-e.1985.0034
出版商:IEE
年代:1985
数据来源: IET
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2. |
On the implementation of sequential circuits with PLA modules |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 132,
Issue 5,
1985,
Page 246-250
J.I.Acha,
J.Calvo,
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PDF (550KB)
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摘要:
In the paper, an algorithm based on Liu methods is developed for the implementation of synchronous sequential machines with PLA modules and D flip-flops. It can be also used for PLA implementation of both asynchronous sequential machines and speed-independent circuits. The method is simple and systematic, and computer programs can be easily developed for its implementation.
DOI:10.1049/ip-e.1985.0035
出版商:IEE
年代:1985
数据来源: IET
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3. |
Syndrome-testable logic design using DSTL arrays for detecting stuck-at and bridging faults |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 132,
Issue 5,
1985,
Page 251-256
A.Pal,
B.Bhattacharya,
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PDF (760KB)
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摘要:
Fault-detection problems in combinational networks design with a novel logic block consisting of a cellular interconnection of AND/OR gates, called DSTL gates (digital summation threshold logic), are considered in the paper. Techniques have been proposed for making these structures easily syndrome testable in order to detect all single stuck-at faults, all bridging faults between any two lines and also for detecting a large number of multiple stuck-at and bridging faults.
DOI:10.1049/ip-e.1985.0036
出版商:IEE
年代:1985
数据来源: IET
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4. |
Aspects of portability of the UNIX shell |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 132,
Issue 5,
1985,
Page 257-264
D.Keefe,
G.M.Tomlinson,
A.J.Wellings,
I.C.Wand,
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PDF (1131KB)
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摘要:
The problems posed by the design and implementation of a command-language interpreter for a subset of the UNIX shell on the PULSE distributed operating system are described. The design of a command processor is addressed as the problem of transferring a user-perceived model of system behaviour from one physical system to another. The major differences between PULSE and UNIX are considered, and next how the shell language may be implemented in terms of the facilities of each system. An important discussion concerns the use of Ada tasks in PULSE and how this affects both the structure and the readability of the resulting program, in this case the shell. It is concluded that the overall structure is not greatly different, but that the use of tasks nevertheless requires careful appreciation of their allocation and termination.
DOI:10.1049/ip-e.1985.0037
出版商:IEE
年代:1985
数据来源: IET
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5. |
Automated synthesis of digital circuits from RT-level description |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 132,
Issue 5,
1985,
Page 265-277
S.Gai,
M.Mezzalama,
P.Prinetto,
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PDF (1198KB)
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摘要:
In the paper a CAD system, Orion, for the automated control-flow based synthesis of synchronous digital circuits will be presented. Orion's goal is to speed up the design process by at least one order of magnitude, relieving the designer from uncreative and error-prone phases. Orion's input is a behavioral description of the circuit, written in a nonprocedural hardware description language (HDL), whereas its output is a structural description, compatible with tools for automatic layout, e.g. those available for PLAs and standard cells. After a detailed analysis of Orion architecture, comparisons will be made with related researches.
DOI:10.1049/ip-e.1985.0038
出版商:IEE
年代:1985
数据来源: IET
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6. |
Automatic determination of overlay structures |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 132,
Issue 5,
1985,
Page 278-288
D.M.Velašević,
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PDF (1275KB)
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摘要:
A concept of the automatic determination of overlay structures is presented. A simple language is designed to support the formal description of software systems subjected to the automatic overlay construction. Two methods for the automatic construction of overlay structures are analysed. The concept is implemented as an interactive system facilitating considerably the construction of overlays.
DOI:10.1049/ip-e.1985.0039
出版商:IEE
年代:1985
数据来源: IET
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