摘要:

A special-purpose computer for processing video signals in radar systems is presented. The main part of the computer is an array ofQprocessing elements (PEs), all driven by the same microprogrammed control block. Each PE handles four bits in parallel, and carries out arithmetic and logic operations on operands from 4–16 bits long. It contains a local memory and an unconventional microprocessor designed to be custom integrated on a 40-pin chip. A set of problem-oriented instructions has been defined, giving efficient implementation of algorithms used in radar computations. The computer can assume different configurations, making it suitable for a large class of radar systems.

DOI:10.1049/ip-e.1980.0022

出版商:IEE    

年代:1980

数据来源: IET

摘要:

In name-space architectures, the mapping of names onto fast registers is a hardware, rather than a software, function. The MU5 computer is an example of such an architecture, having a single-address instruction format with some stacking facilities, and this paper introduces proposed two-store-address and three-store-address architectures developed from MU5 concepts. ISPS descriptions of all three architectures have been written, verified and used in a series of experiments conducted at Carnegie-Mellon University, Pittsburgh, from Manchester University, England, using the ARPA Network. Results are presented of measurements of static and dynamic code usage for a number of benchmark programs run on the ISPS simulation models of these systems, and comparisons between the three architectures are made on the basis of these results.

DOI:10.1049/ip-e.1980.0024

出版商:IEE    

年代:1980

数据来源: IET

摘要:

The Instruction Set Processor (ISP) notation was originally developed as a means of describing formally the behavioural aspects of computer systems. ISPS is a computer language based on this notation, and for which a compiler and simulator have been produced. An ISPS description of the MU5 computer has been written, verified, and used in a series of evaluation experiments conducted at Carnegie-Mellon University (CMU), Pittsburgh, from Manchester University, England, using the ARPA network. The paper presents the important features of the MU5 instruction set and introduces the notation used in ISPS through the essential features of the ISPS description of MU5. Results of benchmark programs run on the ISPS simulation model of MU5 are related to actual results obtained by hardware monitoring of the MU5 processor, and some new MU5 performance figures are given. Results are also presented for the CMU Computer Family Architecture (CFA) project test programs, and some comment is included on the validity of this type of architectural evaluation.

DOI:10.1049/ip-e.1980.0025

出版商:IEE    

年代:1980

数据来源: IET

摘要:

To decode a (255, 223) Reed-Solomon code overGF(28), a fast Fourier-like transform overGF(28) has been developed to compute the syndromes and the error-erasure vectors of the transmitted code words. This new simplified transform decoder is implemented in a program on a digital computer. The (255, 223) Reed-Solomon code overGF(28) is being proposed as a NASA standard for concatenation with a (7, 1/2) conventional code. In a simulation, random code words were corrupted by random error and erasure patterns, and decoded whenever theoretically possible. A matrix of execution times for this new transform decoder under varying sets of errors and erasure patterns is included in the paper. This matrix demonstrates that the speed of the new decoder is between three and seven times faster than the software R—S decoder developed previously by NASA.

DOI:10.1049/ip-e.1980.0026

出版商:IEE    

年代:1980

数据来源: IET

摘要:

The chain code is an attractive and economical method of coding a binary image, but it is not particularly easy to generate. This article describes a hardware/software mechanism for improving the speed of chain-code generation. At the heart of the procedure is an r.o.m. which is used to detect certain (binary) patterns in the input image. The r.o.m. also controls the acquisition of data by an r.a.m.; the result is a set of data triples of the form (xco-ordinate,yco-ordinate, chain-code element) describing a certain subset of the edge points. A software algorithm is then used to ‘thread’ these elemental items together to generate the complete chain-code string. The procedure can accommodate holes and multiblob images.

DOI:10.1049/ip-e.1980.0027

出版商:IEE    

年代:1980

数据来源: IET

摘要:

It is shown how, by augumenting a microprocessor or mincomputer with a relatively small amount of iteratively driven logic, the operation of table lookup using a binary search algorithm can be speeded up by 1½ to 2 orders of magnitude. The approach is very suitable for 1.s.i. implementation as a standard peripheral device for a microprocessor.

DOI:10.1049/ip-e.1980.0028

出版商:IEE    

年代:1980

数据来源: IET