摘要:

The paper is concerned with a multiprocessor computer architecture, which offers a flexible and high-performance system at low cost. The processing elements in the design may be connected as a hierarchy, and the system software supports a virtual memory which may be distributed throughout the processing elements. The principal form of communication is therefore through shared data structures. The paper examines the design of this memory system and considers two approaches for using the architecture, namely as a conventional process-based system and as a dataflow system.

DOI:10.1049/ip-e.1987.0031

出版商:IEE    

年代:1987

数据来源: IET

摘要:

As in binary, a multiple-valued programmable logic array (PLA) realises a sum-ofproducts expression specified by the user. However, in multiple-valued logic, there are many more operations than in binary, and an important question is the choice of operations which provides the greatest number of functions for a given chip area. In this paper, we analyse various PLA configurations using operations realised in the peristaltic multiple-valued CCD technology. We compare a multiple-valued CCD PLA implementation with four other proposed designs and show that there is a significant difference in chip area required to realise the same set of functions. The basis of comparison is the set of 4-valued unary functions.

DOI:10.1049/ip-e.1987.0032

出版商:IEE    

年代:1987

数据来源: IET

摘要:

Vertical migration is a well known technique to improve the performance of a computer system in which the selected primitives (instruction sequences or functions) are moved to a lower level in the software/firmware hierarchy. Concerning the steps to be performed to apply this technique, we have taken into account in the paper the selection problem of vertical-migration candidates. To solve the selection of these sequences which leads to the highest time saving for control-store filling, a suboptimal algorithm which considers the structural aspects (interrelationships) between the candidate sequences is presented. To validate this algorithm, it has been run over a selected high number of different sets of candidate sequences, and the results obtained show that the average deviation between the suboptimal solution and the optimal one is under 5% and, on the other hand, that the computer time and memory space required to evaluate it are drastically reduced.

DOI:10.1049/ip-e.1987.0033

出版商:IEE    

年代:1987

数据来源: IET

摘要:

In realising an N-tap finite impulseresponse (FIR) filter, N multiplications and N – 1 additions must be performed during every sampling interval. The multiplication process can be pipelined easily because there is no recurrence. The (N – l)-port addition process is essentially a vector-reduction process with inherent recurrence and is a bottleneck of hardware utilisation when implemented using a pipelined arithmetic unit. In the paper we present a new pipeline structure for implementing the multiport adder. For an arithmetic pipeline with M segments, our new design achieves the theoretical upper bound on hardware utilisation provided that N ≥ (L + 2)M − 2L+1where L = Int (log2(M)), the largest integer less than or equal to log2(M). This pipeline structure is also useful in pipelined signal-processor design.

DOI:10.1049/ip-e.1987.0034

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The ‘virtual cut-through switching’ method of message transmission in computer communication is modified to achieve further reduction of message transmission delays. A local rerouting feature is also added, so that this ‘modified cut-through switching’ method sustains the ability to adjust the message transmission path in the face of fast fluctuations in traffic-flow conditions. The hardware architecture for the implementation of this method is also presented.

DOI:10.1049/ip-e.1987.0035

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The interference that results from processors attempting to simultaneously access the same main memory in a multiprocessor can be reduced by constructing the memory from separate modules accessible through a crossbar network. The effectiveness of this solution depends on the number of processors and the number of memory modules, and on the parameters of the computation being executed, such as the think time of the processors, the frequency of their access to main memory, and the length of time these accesses are connected to memory. This paper presents a memory-interference model that allows one to evaluate the performance of crossbar-based multiprocessors. The model is a discrete-time model that explicitly describes each processing element's behaviour by means of a semi-Markov process. The chief advantage of the semi-Markov model is its conciseness and its capability of accounting for variance in model parameters. The model is first developed for the case in which memory accesses are directed to each memory module equiprobably. Central to the model is a theorem that gives the residual waiting time experienced by a processor when accessing a busy memory. Comparisons are made with earlier models. These comparisons show the semi-Markov model to be more accurate, particularly in those cases where there is a high degree of variance in the connection time. Finally, the model is generalised to deal with cases where accesses to each memory module are not equiprobable.

DOI:10.1049/ip-e.1987.0036

出版商:IEE    

年代:1987

数据来源: IET